Trench MOS device and process for radhard device

ABSTRACT

A MOSgated device is resistant to both high radiation and SEE environments. The active area of the device is formed of trench devices having a thin gate dielectric on the trench walls and a thicker dielectric on the trench bottoms over the device depletion region. Termination rings formed of ring-shaped trenches containing floating polysilicon plugs surrounds and terminates the device active area.

RELATED APPLICATIONS

[0001] This application claims the priority of Provisional ApplicationSer. No. 60/015,901, filed Apr. 22, 1996. This application is a divisionof Ser. No. 08/818,908 filed Mar. 17, 1997, allowed.

FIELD OF THE INVENTION

[0002] This invention relates to radiation hardened (“radhard”) deviceswhich have improved resistance to damage by large (megarad) doses ofionizing radiation, or by single or plural high energy charged particles(“SEE” particles).

BACKGROUND OF THE INVENTION

[0003] Radiation hardened power MOSFETs and other MOSgated devices foruse in space or other high radiation ambients have conflicting designrequirements for resisting damage due to high doses of ionizingradiation on the one hand, and damage due to even single event highenergy charged particles (“SEE”) on the other hand. Thus, a thin gateoxide is desirable to resist high radiation (megarad) environments,while a relatively thick gate oxide is desirable to resist SEE effects.

[0004] More specifically, it is known that after exposure to a largetotal dose of ionizing radiation a positive charge will build up in thegate oxide to change the device threshold voltage. Further, there is anincrease of interface traps at the silicon/gate oxide boundary. Both ofthese effects are reduced by using a thinner gate oxide, for example,one having a thickness of less than about 900 Å.

[0005] Devices in a high radiation environment, for example, outerspace, are also subject to damage or failure if struck by even a singlehigh energy charged particle. Such charged particles which pass into orthrough the silicon generate a large number of electron-hole pairs inthe depletion region of the device. Some of these charges collect on thegate oxide, resulting in a high potential across the gate oxide. Thus, athicker gate oxide, for example, one thicker than about 1300 Å isdesired to resist SEE failure.

[0006] Because of these diverse requirements, different manufacturingprocesses are used for a “megarad” product, designed for use in a hightotal radiation dose environment and an SEE product which is optimizedfor single particle effects.

[0007] In presently designed vertical conduction, multi-cellular MOSFETproducts, the charge collection at the oxide interface is in the driftregion between cells. The device voltage is set in the charge in theinversion region. Thus, a design trade-off is necessary to set the gateoxide thickness for either a thin gate oxide for good total doseresistance or relatively thicker gate oxide for good SEE resistance.

BRIEF DESCRIPTION OF THE INVENTION

[0008] In accordance with the present invention a MOSgated device (apower MOSFET, IGBT, GTO or other device employing an MOS gate) which hasoptimal oxide thicknesses for both total radiation dose resistance andSEE resistance is provided, using a trench design device. Thus, a knownvertical conduction trench device has an invertible channel region onthe sides of each trench, while the drift region lies along and underthe bottoms of the trenches. Consequently, the gate oxide thickness atthe walls of the trench can be relatively thin, and less than about 900Å (preferably about 500 Å) for optimal total dose resistance, while thebottoms of the trench have a relatively thick oxide liner, for example,greater, than about 1300 Å (and preferably about 3000 Å) for optimalresistance to breakdown by single event effects.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is a cross-section of an otherwise conventional trench typepower MOSFET with diverse thickness oxides in the wells to optimizetotal radiative dose resistance and SEE resistance in accordance withthe invention.

[0010]FIG. 1A shows another and preferred embodiment of the invention inwhich a p+ conductive trench is added between spaced trenches containingthe invertible sidewall channels.

[0011]FIGS. 2 through 8 show a cross-section of the device of FIG. 2 asit is manufactured and following various mask steps.

DETAILED DESCRIPTION OF THE DRAWING

[0012] Referring first to FIG. 1, there is shown a cross-section of asmall portion of a multicell trench process vertical conduction powerMOSFET device which contains the features of the present invention. Morespecifically, a monocrystalline silicon chip 10 consists of an N+support body 11 which has an N(−) epitaxially formed layer 12 thereon. AP type channel region 13 is diffused into the surface of region 13 to adepth of about 1 to about 1.5 microns, followed by the diffusion ofspaced N+ source regions 14 to 19. A plurality of parallel elongatedwells or trenches 20, 21, 22 and 23 are then etched into the uppersurface of layer 12 to a depth, for example, of about 2 microns. Wells20 to 23 may also be formed as separate symmetric cells distributed overthe surface of region 12. The wells have a width of about 1.5μ and aseparation of about 1μ.

[0013] Thick oxide layers 30 to 33 are grown or deposited on the bottomsof wells 20 to 23 respectively.

[0014] In order to grow a thick oxide at the bottom of the trench, itmay be first implanted to damage the bottom surface and to enhance theoxide growth rate at the bottom. The oxide can also be deposited by amethod having good step coverage, such as low pressure chemical vapordeposition. As another process, after depositing oxide in the wells, theoxide may be etched to reduce the thickness of layers, preferably toless than about 3000 Å and to expose the side walls of grooves 20 to 23.Thereafter, gate oxide layers 40 to 43 are grown on the side walls ofgrooves 20 to 23 to a thickness of about 500 Å.

[0015] Thereafter, the wells 20 to 23 are filled with conductive N+polysilicon layers 50 to 53 which act as the conductive gates for thedevice and which are laterally interconnected (not shown) and have anappropriate common gate connection terminal 60. The tops of polysiliconlayers 50 to 53 are covered by patterned oxide insulation layers 60 to63 respectively. The upper surface of the device then receives analuminum source electrode 70 which is connected to the exposed regionsof source regions 14 to 17, and to the P regions 13 between the sources.A drain electrode 71 is formed on the bottom of chip 10.

[0016] Numerous manufacturing processes can be used to make the deviceof FIG. 1. The essential result is that the oxide layers 30 to 33 arerelatively thick, for example, greater than 1300 Å, and are optimizedfor SEE resistance, while the gate oxide thickness on the walls of thetrenches is thinner than the bottom oxide layers and is optimized forbest radiation dose resistance and is less than about 900 Å.

[0017] Referring next to FIG. 1A, a second preferred embodiment of theinvention is shown, in which elements similar to those of FIG. 1 havethe same identification numeral. In FIG. 1, however, added trenches 80to 82 are formed between pairs of trenches 20, 21, 22 and 23. Forexample, trench 81 is between trenches 20 and 21 and trench 82 isbetween trench 21 and trench 22 (not shown in FIG. 1A). Trenches 80, 81and 82 are filled with conductive P+ polysilicon, and make good contactto source contact 70. The P+ polysilicon diffuses into the trench walls,as shown in dotted lines in FIG. 1A. A plurality of spaced grooves likegroove 80 form the device termination as later shown in FIG. 8.

[0018]FIGS. 2 through 8 show the preferred manufacturing process andshow the device being processed at different successive stages ofmanufacture. Thus, FIG. 2 shows a small portion of the chip or waferbeing processed after the first mask. An N(−) epitaxial region 12 isprovided. For a 500 volt part epi 12 has a thickness of 48 to 58 micronsand a resistivity of 18.2 ohm cm. Region 12 is deposited on anunderlying N(+) substrate, not shown in FIG. 2. An oxide 100 having athickness of about 5000 Å has been grown on the device terminationregion in FIG. 2, while the active area has received a boron implant at80 KEV and about 6.0E 13, driven to a depth of about 1.5 microns to formP(−) region 13.

[0019] The device topology may employ elongated parallel wells. However,the topology in FIGS. 2 to 8 is for a cellular device, and the wells 113to 116 are formed as part of a symmetrical grid of polygonal wells.Rings 111 and 112 are continuous rings which surround the active area.

[0020]FIG. 3 shows the structure of FIG. 2 after mask 2 in which aplurality of wells, including termination wells 110 to 112 (20termination rings may be used for a 600 volt device) and active areawells 113 to 116 are etched to a depth of about 2 microns with a spacingof about 1 micron and a width of about 1 to 1½ microns.

[0021]FIG. 4 shows the structure of FIG. 3 after mask 3, in which anoxide layer is grown and etched to form silicon dioxide plugs 120 and121 in alternate active area wells 113 and 115.

[0022] Thereafter and as shown in FIG. 5, a polysilicon layer isdeposited to fill the termination trenches 130 and 131 and the alternatetrenches in the active area 132 and 133, and to cover the surface. Aboron implant of 1E16 at 80 KeV is applied to the surface of thispolysilicon. A high temperature diffusion is used to distribute thisboron throughout the polysilicon and into the silicon to the dottedline. The rapid diffusion of boron in polysilicon as compared to singlecrystal silicon results in the p-n junction formed by this borondiffusion being deeper than it is wide. The polysilicon surface isetched to the upper surface of layer 12 to leave only plugs 130 to 133in place. Thereafter, the oxide plugs 120, 121 and other oxides on thedevice surface are etched until the oxide plugs 120 and 121 have beenetched down to about 3000 Å to define thick oxide bottom layers 135 and136 in alternate wells 113 and 115 respectively.

[0023] Thereafter and as shown in FIG. 6 a thin gate oxide, 140 forexample, 500 Å is grown over all exposed silicon, including the interiorwalls of grooves 113 and 115. These correspond to thin gate oxide layerportions 150, 151, 152, and 153 in FIG. 6.

[0024] Thereafter, a polysilicon deposition is applied which fills thetrenches and covers the surface of the die. A suitable mask 4 is appliedwhich defines the gate busses (not shown). The polysilicon is etched tothe surface of the chip except in the gate bus areas, leavingpolysilicon plugs in trenches 160 and 162.

[0025] As next shown in FIG. 7, the surface of the wafer is masked withmask 5 and N+ source regions 180 and 181 of ring-shaped topology and thepolysilicon plugs 160 and 161 are implanted with phosphorus at a dose of5E15 and an energy of 80 KEV. The sources 180 and 181 may have a depthof about ½ micron.

[0026] Sources 180 and 181 are shown in FIG. 7 for a hexagonal topology,although they could be in strip form. A polygonal topology is preferredfor low voltage devices and a line topology is preferred to highervoltage ratings.

[0027]FIG. 8 shows the structure of FIG. 7 following the 6th mask step.Thus, the surface of the wafer first has an interlayer 190 of lowtemperature oxide (“LTO”) formed thereon. A mask step then allows theetching of the LTO 190 and underlying gate oxide 140 to define thepattern shown in FIG. 8, with LTO 190 covering the P+ poly terminationrings including ring 130, and LTO buttons 191 and 192 covering the N+poly plugs 160 and 161, but exposing the P+ poly plugs 131, and 132 andtheir surrounding source rings 180 and 182.

[0028] Source metallizing can then be applied to the device surface, asshown in FIG. 1A.

[0029] It will be noted that in the final device, that the P+ diffusionsin poly plugs 131 and 132 are self aligned to the N+. Therefore, the P+can be very close to the channel without invading the channel.

[0030] The termination rings 110 and 111 and other similar concentricspaced rings which extend to the edge of the die (not shown) are neededto control the very high electric field at the corner of the innermosttrenches of the active region, such as trench 112 in FIG. 8. That is theelectric field at the corner of the P⁺ diffusion from the walls oftrench 112 is very high and will cause device breakdown at a voltagelower than could be obtained with the silicon used. Other terminationscould be used, for example, separate deep P diffusions.

[0031] In accordance with an important aspect of the invention, a novelfloating ring termination structure is provided using poly filledtrenches 110 and 111 with P⁺ doping, which are formed by the sameprocess steps used to form the active region, and without requiringadded mask steps.

[0032] The precise number of trenches used and their spacing can beoptimized for each voltage rating. Thus, more rings with wider spacingare used for higher voltage devices and fewer rings at closer spacingare used for lower voltage ratings. For example, for a high voltagetermination, the rings may be spaced by 3 to 5 microns. For a lowervoltage termination, the rings could be spaced from 1.5 to about 2microns. The wider spaced rings will break down at a lower voltage thancloser spaced rings.

[0033] Significantly, when using poly filled trench rings, the breakdownvoltage in any part of the device can be controlled by their spacing, toensure that breakdown occurs first in the termination ring region andnot in the active area of the device. Thus, by putting two ringssufficiently far, breakdown will first occur in the area of the tworings, permitting a turn off of the device before permanent damage canoccur.

[0034] More particularly, in a power MOSFET, IGBT, or GTO device, it maybe preferred to have breakdown first occur underneath the source bondpad (a portion of source 70 in FIG. 1A to the left of the drawing andremoved from the active area) instead of at the active cell region. Thisminimizes the generation of minority carriers in the active area whichcan cause the turn on of parasitic bipolar devices which might latch on,resulting in device failure.

[0035] The appropriate spacing of the termination trenches relative tothe device design can make the device more rugged in applications whereavalanche voltage can occur.

[0036] In the above description of the invention, an N-channel devicehas been described. Obviously, the concentration regions can be reversedto produce a P-channel device.

[0037] Although the present invention has been described in relation toparticular embodiments thereof, many other variations and modificationsand other uses will become apparent to those skilled in the art. It ispreferred, therefore, that the present invention be limited not by thespecific disclosure herein, but only by the appended claims.

What is claimed is:
 1. A gated MOS device which is resistant to failurein both high radiation environments and in SEE environments; said gatedMOS device comprising a silicon die having a plurality of spacedtrenches therein; each of said spaced trenches being defined by at leastpartly vertical walls joined at their bottoms by respective trenchbases; at least portions of the areas of said vertical walls having aMOS gate dielectric thereon, said bases of said trenches having a bottomdielectric thereon; said gate dielectric having a thickness chosen tooptimize resistance to high radiation effects; said bottom dielectrichaving a thickness greater than that of said gate dielectric and athickness which is optimal for SEE resistance.
 2. The gated MOS deviceof claim 1 in which said plurality of trenches are filled withconductive polysilicon which acts as a gate electrode.
 3. The gated MOSdevice of claim 1 in which said gate dielectric and said bottomdielectric are both silicon dioxide.
 4. The gated MOS device of claim 3wherein said gate dielectric has a thickness which is less than 900 Å.5. The gated MOS device of claim 3 wherein the thickness of said bottomdielectric is greater than about 1300 Å.
 6. The gated MOS device ofclaim 4 wherein said gate dielectric thickness is about 500 Å.
 7. Thegated MOS device of claim 5 wherein said gate dielectric thickness isabout 500 Å.
 8. The gated MOS device of claim 5 wherein the thickness ofsaid bottom dielectric is about 3000 Å.
 9. The gated MOS device of claim6 wherein the thickness of said bottom dielectric is about 3000 Å.
 10. Atrench MOS gated device which has improved resistance to both highradiation and SEE comprising a silicon wafer of one of the conductivetypes having a plurality of spaced shallow active trenches containingrespective gate structures and a plurality of intermediate trenches eachdisposed between a respective pair of active trenches; each of saidtrenches having at least partly vertical walls joined at their bottomsby trench bottoms; each of said trenches containing a gate structurehaving a gate dielectric on at least portions of their said verticalwalls, a bottom dielectric on their bottoms and a conductive polysiliconplug which acts as a gate electrode which contacts at least the interiorsurface of said gate dielectric; each of said intermediate trencheshaving a shallow diffusion of the opposite conductivity extending fromtheir walls and bottoms and being filled with a conductive polysilicon;the spaces between each of said trenches containing a channel region ofthe opposite conductivity and an upper source diffusion in contact withsaid polysilicon plugs in said trenches containing said gate structure;and a common source contact contacting each of said source regions andeach of said conductive plugs in each of said intermediate trenches; acommon gate electrode connected to each of said conductive plugs in eachof said trenches containing a gate structure and a drain contactconnected to the drift region beneath said trenches.
 11. The device ofclaim 10 in which said polysilicon plugs in said trenches containing agate structure is of said one of said conductivity types, and in whichsaid polysilicon plugs in said intermediate trenches is of the oppositeconductivity type.
 12. The device of claim 10 wherein all of saidtrenches are parallel elongated trenches.
 13. The device of claim 10wherein at least a plurality of said trenches containing a MOS gatedstructure are polygonal in topology and are symmetrically spaced anddisposed over the surface of said silicon wafer; said source regionssurrounding respective ones of said trenches containing a MOS gatedstructure; said intermediate trenches consisting of a trench of latticeshape in topology which extends in the space defined between spacedpolygonal trenches.
 14. The device of claim 12 in which said polysiliconplugs in said trenches containing a gate structure is of said one ofsaid conductivity types, and in which said polysilicon plugs in saidintermediate trenches is of the opposite conductivity type.
 15. Thedevice of claim 13 in which said polysilicon plugs in said trenchescontaining a gate structure is of said one of said conductivity types,and in which said polysilicon plugs in said intermediate trenches is ofthe opposite conductivity type.
 16. The device of claim 10 wherein thethickness of said gate dielectric is chosen to optimize resistance tohigh radiation effects and wherein the thickness of said bottomdielectric is chosen to optimize resistance to SEE.
 17. The device ofclaim 11 wherein the thickness of said gate dielectric is chosen tooptimize resistance to high radiation effects and wherein the thicknessof said bottom dielectric is chosen to optimize resistance to SEE. 18.The gated MOS device of claim 16 in which said gate dielectric and saidbottom dielectric are silicon dioxide.
 19. The gated MOS device of claim18 wherein said gate dielectric has a thickness which is less than 900Å.
 20. The gated MOS device of claim 18 wherein the thickness of saidbottom dielectric is greater than about 1300 Å.
 21. The gated MOS deviceof claim 19 wherein the thickness of said bottom dielectric is greaterthan about 1300 Å.
 22. A termination structure for a gated MOS devicehaving an active area; said active area consisting of a plurality ofspaced trenches in a common silicon die of one of the conductivitytypes, each of said trenches containing a respective MOS gate structure;the exterior trenches in said active area having a relatively highelectric field at their bottom outer corners; said termination structurecomprising a plurality of concentric ring-shaped trenches surroundingsaid active area and being spaced between said active area and theperipheral edge of said die; each of said plurality of ring-shapedtrenches having a diffusion extending from their walls and bottom whichis of the opposite conductivity type; each of said plurality ofring-shaped trenches having a conductive polysilicon plug of aconductivity of the opposite conductivity type; said active area havinga common source contact; said plurality of ring-shaped trenches beinginsulated from said source contact and comprising floating rings. 23.The termination structure of claim 22 wherein said concentric rings havea predetermined spacing from one another.
 24. The termination structureof claim 23 wherein the spacing between said rings is selected to causebreakdown due to high reverse voltage to occur between said rings beforeit occurs in said active area.
 25. The device of claim 10 which furthercontains a termination structure; said plurality of trenches containinga gate structure and said plurality of intermediate trenches defining anactive area; said termination structure comprising a plurality ofconcentric ring-shaped trenches surrounding said active area andextending radially from said active area toward the edge of said die;each of said plurality of ring-shaped trenches having a diffusionextending from their walls and bottom which is of the oppositeconductivity type; each of said plurality of ring-shaped trenches havinga conductive polysilicon plug of a conductivity of the oppositeconductivity type; said plurality of ring-shaped trenches beinginsulated from said source contact and comprising floating rings. 26.The termination structure of claim 25 wherein said concentric rings havea predetermined spacing from one another.
 27. The termination structureof claim 26 wherein the spacing between said rings is selected to causebreakdown due to high reverse voltage to occur between said rings beforeit occurs in said active area.
 28. The device of claim 16 which furthercontains a termination structure; said plurality of trenches containinga gate structure and said plurality of intermediate trenches defining anactive area; said termination structure comprising a plurality ofconcentric ring-shaped trenches surrounding said active area andextending radially from said active area toward the edge of said die;each of said plurality of ring-shaped trenches having a diffusionextending from their walls and bottom which is of the oppositeconductivity type; each of said plurality of ring-shaped trenches havinga conductive polysilicon plug of a conductivity of the oppositeconductivity type; said plurality of ring-shaped trenches beinginsulated from said source contact and comprising floating rings.